1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to an ESD protection circuit suitable for applying in an integrated circuit (IC) with separated power domains.
2. Description of the Prior Art
ESD is one of the most important reliability issues for IC products, which must be taken into consideration during the design phase of all ICs. With the advance of IC fabrication technologies, more and more circuit blocks are integrated in a single chip. In such a system-on-chip (SoC) application, the interface circuits in ICs with separated power domains are often damaged by ESD stresses.
A variety of ESD detection circuits for ICs with separated power domains were proposed. FIG. 1 and FIG. 2 respectively illustrate the traditional ESD protection circuits. In FIG. 1, the labels VDD1 and VSS1 represent power rails in a first power domain; VDD2 and VSS2 represent power rails in a second power domain. The PMOS MPESD and the NMOS MNESD are used to protect the interface circuits between the two power domains.
Generally, ESD occurs when one pin of an IC is grounded and another pin of the IC contacts an electrostatically pre-charged object. In the circuit of FIG. 1, when VDD1 is zapped by a positive ESD stress with VSS2 grounded, the ESD energy will be conducted to the gate terminals of MP2 and MN2 through MP1. MNESD, which is a gate-grounded NMOS (GGNMOS), will be turned on to clamp the gate potential of MN2. Therefore, MN2 can be protected against ESD damages.
For the circuit in FIG. 1, when VDD1 is zapped by a positive ESD stress with VDD2 grounded, the parasitic P+/N-well diode (between the signal line and VDD2) in MPESD will clamp the gate potential of MP2 to protect MP2 against ESD damages. Similarly, when VSS1 is zapped by a negative ESD stress with VSS2 grounded, the parasitic N+/P-well diode (between VSS2 and the signal line) in MNESD will clamp the gate potential of MN2 to protect MN2 against ESD damages. Further, when VSS1 is zapped by a negative ESD stress with VDD2 grounded, the gate-VDD PMOS (GDPMOS) MPESD will be turned on to clamp the gate potential of MP2. Therefore, MP2 can be protected against ESD damages.
In FIG. 2, two diodes DP and DN are used to protect MP2 and MN2. When the ESD overstress voltage appears at the gate terminals of MP2 and MN2, DP and DN will clamp the voltage across the gate oxides of MP2 and MN2. With the power-rail ESD clamp circuit between VDD2 and VSS2, MP2 and MN2 can be protected against ESD damages.
FIG. 3 illustrates an ESD protection circuit proposed in “ESD protection design to overcome internal damages on interface circuits of a CMOS IC with multiple separated power pins” reported by M.-D. Ker, C.-Y. Chang, and Y.-S. Chang in IEEE Trans. Components and Packaging Technologies, vol. 27, no. 3, pp. 445-451, September 2004. In this circuit, two ESD clamp devices MNESD1 and MNESD2 are placed between VDD2 and the signal line, and between the signal line and VSS2, respectively.
When VSS1 is zapped by a negative ESD stress with VDD2 grounded, MNESD1 will be turned on to clamp the gate potential of MP2. When VSS1 is zapped by a negative ESD stress with VSS2 grounded, the parasitic N+/P-well diodes (between VSS2 and the signal line) in MNESD1 and MNESD2 will clamp the gate potential of MN2 to protect MN2. The gate terminal of MNESD1 is connected to its source terminal, so MNESD1 is turned off under normal circuit operating conditions.
When VDD1 is zapped by a positive ESD stress with VSS2 grounded, the GGNMOS MNESD2 will be turned on to clamp the gate potential of MN2 to protect MN2 against ESD damages. When VDD1 is zapped by a positive ESD stress with VDD2 grounded, MNESD1 will act as a diode-connected NMOS to clamp the gate potential of MP2.